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  d ata s heet ML53812-2 h.100/h.110 ct bus system interface and time-slot interchange january 2000 o k i n e t w o r k p r o d u c t s
oki semiconductor revision history september 1999 320101-005 previous release january 2000 320101-006 timing tables altered on page 50: local clock and frame synchronization timing, local clock to ct bus clock skew, and local serial stream timing timing diagram (figure 11) atered on page 51: local clock and frame synchronization timing
oki semiconductor contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ML53812-2 176-pin lqfp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ct bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin continuity test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 analog pll test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 analog pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 slave pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 master pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 reference master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 local clock and frame sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 local streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ct bus streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ct_d disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 diagnostic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 gpio ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 message channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 microprocessor address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 command/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 internal address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 device id registers (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 stream switch routing registers, ar = 1007h:1000h (ch. 7:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 stream switch connection mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 transmit switch routing registers, ar = 20ffh:2000h (ch. 255:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 receive switch routing registers, ar = 30ffh:3000h (ch. 255:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 indirect transmit switch parallel access registers, ar = 40ffh:4000h (ch. 255:0) . . . . . . . . . . . . . . . . . . . 45 indirect receive switch parallel access registers, ar = 50ffh:5000h (ch. 255:0) . . . . . . . . . . . . . . . . . . . . 45 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 h.100/h.110 bus timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 clock skew requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ML53812-2 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 lqfp176 package outlines and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 lqfp176 mounting pad reference measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
n n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC oki semiconductor
1 oki semiconductor ML53812-2 h.100/h.110ct bus system interface and time slot interchange 1.0 description the ML53812-2 is a complete ct bus system interface and time slot interchange device that provides a cost-effective connection between a computer boards telephony interfaces or signal processing resources and the ct bus. the ML53812-2 is an evolution of existing time-slot interchange ics which offers seam- less interoperability with scbus devices. a key element in computer telephony (ct) equipment is the auxiliary telecom bus. most manufacturers of high-capacity ct equipment have used one or more types of telecom buses to transport and switch low-latency communications traffic between boards within the computer, bypassing the computers main i/o and memory buses. to simplify the integration of devices that incorporate a telecom bus, the enterprise computer telephony forum (ectf) developed a standard bus (h.100/h.110 ct bus?) that provides compatibility modes with the most prevalent telecom buses today (scbus? and mvip-90?), as well as the capacity and feature set needed to support the next generation of high capacity ct servers. the new ct bus is embraced by dialogic under the signal computing system architecture? (scsa?) umbrella of open standards for building interoperable ct systems. the ML53812-2 runs in both 4 mhz and 8 mhz scbus modes and supports the switching features needed to integrate ct bus devices with 4 mhz scbus, 8 mhz scbus, and 2 mhz mvip-90 devices. because the h.100/h.110 ct bus uses an identical switching model and clock speeds to that used for the scbus, developers have unparalleled flexibility in integrating these two types of devices, or in transition- ing from one type to the other. the ML53812-2 takes full advantage of the mandatory and optional features defined in the ectf h.100 and h.110 interoperability specifications. it is a non-blocking 512 x 4096 time slot switch, interfacing up to 512 ports on its parent device to any of the 4096 time slots on the new ct bus. the high number of local time slots available makes it easier to design high-density ct hardware, supporting as many as eight net- work interfaces or 256 voice processing ports per chip. this powerful chip is offered in an ultra slim profile (176-pin lqfp package, with a 24 mm x 24 mm x 1.4 mm body size) that makes it possible to mount the chip on either side of the board. the chip is fully soft- ware programmable, and can be controlled by a variety of microprocessors, including intel and motorola in both multiplexed and nonmultiplexed modes.
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 2 oki semiconductor 2.0 features 2.1 applications ? low and high-density computer telephony hardware (pci and cpci platforms) ? enhanced service platforms ? private branch exchanges (pbxs) ? wireless base stations ? internet telephony systems ? digital trunking equipment ? high functionality, low cost implementation of the ectf h.100/h.110 interoperability specifications. ? simple to connect pci and cpci? board-level circuitry to the universally accepted ct bus?. ? ultra slim profiling (176-pin lqfp package). ? up to 512 programmable connections (256 transmit and 256 receive) to any of the 4096 time slots on the h.100/h.110 ct bus. ? 8-channel stream-to-stream switching for data stream connections at variable rates. ? implementation of all compatibility signals for complete interoperability with existing 4 mhz scbus?, 8 mhz scbus, 2 mhz mvip-90? devices, and h-mvip?. ? provides reliable clock synchronization for network-grade connection to digital network interfaces. ? supports all h.100/h.110 ct bus clock fallback features. ? choice of constant or minimum switching delay on a per time slot basis. ? 3.3 v i/o with 5 v tolerant input. ? supports multiplexed and nonmultiplexed address/data bus modes for both intel and motorola microprocessors. ? supports ct bus optional message channel interface, for both h.100 (pci) and h.110 (cpci) applications. ? supports a variety of framing formats via a configurable local bus. ? efficient microprocessor interface access to local and ct bus data streams through direct parallel access to/from transmit and receive switch.
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 3 oki semiconductor 3.0 pin configuration figure 1. ML53812-2 176-pin lqfp pin con?guration 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 4 oki semiconductor 3.1 ML53812-2 176-pin lqfp pin assignment [1] 1. in this document, signals ending with _n are active low (eg. cs_n). note that in the h.100/h110 specification, active low is indicated with a preceding forward slash (eg. /cs). pin pin name pin pin name pin pin name pin pin name pin pin name pin pin name pin pin name 1 vddc 27 d_6 53 vsso 79 vddo 105 ct_d_9 131 ct_d_25 157 l_si_6 2 ale 28 a_6 54 appl_clkref 80 ct_frame_b_n 106 ct_d_10 132 vssc 158 l_si_7 3 vddo 29 d_7 55 apll_test 81 vsso 107 vddo 133 vddc 159 vsso 4 cs_n 30 a_7 56 tms 82 ct_netref_2 108 ct_d_11 134 ct_d_26 160 l_so_0 5 rd_n 31 a_8 57 tck 83 ct_netref_1 109 vsso 135 vddo 161 l_so_1 6 wr_n 32 a_9 58 trst_n 84 vddo 110 ct_d_12 136 ct_d_27 162 l_so_2 7 vsso 33 nc 59 tdi 85 ct_c8_a 111 ct_d_13 137 vsso 163 l_so_3 8 reset 34 vddo 60 tdo 86 vsso 112 vddo 138 ct_d_28 164 vddo 9 i_n 35 l_netref_0 61 vddo 87 ct_frame_a_n 113 ct_d_14 139 ct_d_29 165 l_so_4 10 int 36 l_netref_1 62 mc_txd 88 vssc 114 vsso 140 vddo 166 l_so_5 11 vddo 37 l_netref_2 63 mc_rxd 89 vddc 115 ct_d_15 141 ct_d_30 167 l_so_6 12 d_0 38 l_netref_3 64 mc_clk 90 ct_d_0 116 ct_d_16 142 ct_d_31 168 l_so_7 13 a_0 39 vsso 65 vsso 91 vddo 117 vddo 143 vsso 169 vsso 14 d_1 40 l_netref_4 66 c16_neg_n 92 ct_d_1 118 ct_d_17 144 gpio_0 170 l_clk_0 15 a_1 41 l_netref_5 67 c16_pos_n 93 ct_d_2 119 ct_d_18 145 gpio_1 171 l_fs_0 16 vsso 42 l_netref_6 68 vddo 94 vsso 120 vsso 146 vddo 172 l_clk_1 17 d_2 43 l_netref_7 69 c4_n 95 ct_d_3 121 ct_d_19 147 gpio_2 173 l_fs_1 18 a_2 44 vssc 70 c2 96 ct_d_4 122 vddo 148 gpio_3 174 ct_d_disable 19 d_3 45 vddc 71 vsso 97 vddo 123 ct_d_20 149 vsso 175 test 20 a_3 46 vddo 72 sclkx2_n 98 ct_d_5 124 vsso 150 l_si_0 176 vssc 21 vddo 47 apll_vddo 73 sclk 99 vsso 125 ct_d_21 151 l_si_1 22 d_4 48 apll_vddc 74 vddo 100 ct_d_6 126 ct_d_22 152 l_si_2 23 a_4 49 appl_pc 75 fr_comp_n 101 vddo 127 vddo 153 l_si_3 24 d_5 50 appl_vco 76 ct_mc 102 ct_d_7 128 ct_d_23 154 vddo 25 a_5 51 appl_vssc 77 vsso 103 ct_d_8 129 ct_d_24 155 l_si_4 26 vsso 52 apll_vsso 78 ct_c8_b 104 vsso 130 vsso 156 l_si_5
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 5 oki semiconductor 4.0 signal descriptions signal description [1] name description d_[7:0] microprocessor data bus. (i/o, ttl schmitt, 8 ma, 5v tolerant) a_ [9:0] microprocessor address bus. (input, ttl schmitt, 5v tolerant) ale (as) intel bus mode - address latch enable. motorola bus mode - address strobe. the microprocessor address bus a[9:0] is lat ched internally on the falling edge of this signal. (input, ttl schmitt, 5v tolerant) cs_n chip select. this active low signal selects the ML53812-2 for a microprocessor read or write operation. (input, ttl schmitt , 5v tolerant) rd_n (strb_n) intel bus mode - microprocessor bus read. motorola bus mode - microprocessor bus strobe. (input, ttl schmitt, 5v t olerant) wr_n (r/w_n) intel bus mode - microprocessor bus write. motorola bus mode - microprocessor bus read/write signal. (input, ttl schmitt, 5v tolerant) reset reset. this active high input signal initializes the microprocessor interface, configuration, and routing registers. (inpu t, ttl schmitt, 5v tolerant) i_n (m) microprocessor bus mode. when this input is low, intel bus mode is selected. when this input is high, motorola bus mode is selected. (input, ttl schmitt, 5v tolerant) ct_d_disable ct_d global disable. (i/o, ttl schmitt, 8 ma, 50 k pull up, 5v tolerant) l_netref_[7:0] local network reference [7:0] input. (input, ttl schmitt, 50 k pull up, 5v tolerant) l_si_[7:0] local bus serial input data input. (input, ttl schmitt, 50 k pull up, 5v tolerant) mc_txd message channel transmit data input. (input, ttl schmitt, 50 k pull up, 5v tolerant) apll_clkref analog pll clock reference input. (input, ttl schmitt, 50 k pull up, 5v tolerant) apll_vddo +3.3 volt analog pll i/o power supply apll_vddc +3.3 volt analog pll core power supply apll_pc analog pll phase comparator analog output apll_vco analog pll vco analog input apll_vssc analog pll core ground apll_vsso analog pll i/o ground apll_test analog pll test enable input. (input, ttl schmitt, 50 k pull up, 5v tolerant) test test select. this input enables the pin continuity test. (input, ttl schmitt, 50 k pull up, 5v tolerant) tms test access port mode select. (input, ttl schmitt, 50 k pull up, 5v tolerant) tck test access port clock. (input, ttl schmitt, 50 k pull up, 5v tolerant) trst_n test access port reset. (active low). (input, ttl schmitt, 50 k pull up, 5v tolerant) tdi test access port data input. (input, ttl schmitt, 50 k pull up, 5v tolerant) int interrupt output. (i/o, ttl schmitt, 50 k pull up, 8 ma, 5v tolerant) ct_d_[31:0] ct bus serial data streams. (i/o, pci, 5v tolerant) ct_frame_a_n ct bus "a" frame sync. (i/o, ttl schmitt, 24 ma, 5v tolerant) ct_c8_a ct bus "a" 8 mhz clock. (i/o, ttl schmitt, 24 ma, 5v tolerant) ct_netref_1 ct bus network reference 1. (i/o, pci, 5v tolerant) ct_netref_2 ct bus network reference 2. (i/o, pci, 5v tolerant) ct_frame_b_n ct bus "b" frame sync. (i/o, ttl schmitt, 24 ma, 5v tolerant) ct_c8_b ct bus "b" 8 mhz clock. (i/o, ttl schmitt, 24 ma, 5v tolerant) ct_mc ct bus message channel. (i/o, ttl schmitt, 24 ma, 5v tolerant)
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 6 oki semiconductor fr_comp_n compatibility frame sync used by scbus, mvip-90, and h-mvip. (i/o, ttl schmitt, 24 ma, 5v tolerant) sclk scbus clock. (i/o, ttl schmitt, 24 ma, 5v tolerant) sclkx2_n scbus x2 clock. (i/o, ttl schmitt, 24 ma, 5v tolerant) c2 mvip-90 2.048 mhz clock. (i/o, ttl schmitt, 6 ma, 5v tolerant) c4_n mvip-90 4.096 mhz clock. (i/o, ttl schmitt, 6 ma, 5v tolerant) c16_pos_n h-mvip 16.384 mhz positive active low clock. high to low transition on frame boundary. (i/o, ttl schmitt, 24 ma, 5v to lerant) c16_neg_n h-mvip 16.384 mhz negative active low clock. low to high transition on frame boundary. (i/o, ttl schmitt, 24 ma, 5v to lerant) l_clk_1 local bus clock 1. (i/o, ttl schmitt, 24 ma, 50 k pull up, 5 v tolerant) l_fs_1 local bus frame sync 1. (i/o, ttl schmitt, 24 ma, 50 k pull up, 5v tolerant) l_clk_0 local bus clock 0. (i/o, ttl schmitt, 24 ma, 50 k pull up, 5 v tolerant) l_fs_0 local bus frame sync 0. (i/o, ttl schmitt, 50 k pull up, 24 ma, 5v tolerant) l_so_[7:0] local bus serial output data streams. (i/o, ttl schmitt, 50 k pull up, 8 ma, 5v tolerant) mc_clk message channel clock output. (i/o, ttl schmitt, 50 k pull up, 6 ma, 5v tolerant) mc_rxd message channel receive data output. (i/o, ttl schmitt, 50 k pull up, 6 ma, 5v tolerant) gpio_[3:0] general purpose i/o ports. (i/o, ttl schmitt, 24 ma, 50 k pull up, 5v tolerant) tdo test access port data output. (output, 6 ma, 5v tolerant) nc no connect vddo +3.3 volt i/o power supply vsso i/o ground vddc +3.3 volt core power supply vssc core ground 1. signals ending in _n are active low. signal description [1] name description
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 7 oki semiconductor 5.0 functional description the ML53812-2 has the following interfaces: 5.1 local bus the local bus consists of up to eight serial input ports and eight serial output ports, totalling 512 possible local bus connections to the ct bus. the input and output ports can be configured independently as two groups of four 2 mb/s streams, two 4 mb/s streams, or one 8 mb/s stream. the chip includes two inde- pendent, configurable local clock and frame synchronization signals. the local clocks have configurable polarity and frequency that can be set to 2 mhz, 4 mhz, 8 mhz, or 16 mhz regardless of local stream data rate. the local frame syncs also have a configurable polarity and can be set to use one of three fram- ing formats (early, straddle, or late). to transfer data to and from the local bus, the ML53812-2 allows the user to select a minimum delay or constant delay buffer mode on a per channel basis. in the minimum delay mode, the input-output buffer transfer occurs on the next 2 mb/s time slot boundary, reducing any potential channel delay for classic voice processing applications. in the constant delay mode, the buffer transfer occurs at the frame bound- ary for bundling and proper switching of wide-band data, for data sent on the isdn h channel. ? microprocessor interface ? local serial data in ? local serial data out ? local timing ? analog pll reference clock ? ct bus timing ? ct bus serial data figure 2. block diagram 8 channel stream switch 256 x 4096 transmit switch master digital pll 4352 x 256 receive switch slave digital pll configuration & routing register analog pll local connect ct bus serial data ct bus timing 131.072 mhz internal timing internal control microprocessor interface apll reference clock local timing local serial data out local serial data in
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 8 oki semiconductor 5.2 ct bus the ML53812-2 provides access to all 4096 ct bus time slots. the upper 16 data lines run at 8 mb/s, while the lower 16 data lines can be configured, in groups of four, to run at 8 mb/s, 4 mb/s, or 2 mb/s for compatibility with scbus and mvip-90 devices. the chip uses an internal analog phase locked loop (pll) as a rate multiplier to produce a 131.072 mhz internal clock locked to a variety of reference frequencies. this high frequency internal clock provides fine grained correction steps (7.6 ns) for the master and slave digital plls. the main ct bus network ref- erence signal can be configured to run at 8 khz, 1.544 mhz, or 2048 mhz. the timing for the ct bus can be configured to be derived from the local clock and frame sync signals to allow multiple chips to be con- nected to the ct bus without overloading the reference clock line. the ML53812-2 incorporates internal master digital pll circuitry that is designed to meet the jitter atten- uation, holdover and maximum time interval error (mtie) requirements of 62411 stratum 3,4 and 4e. this enables the ML53812-2 to be well suited for developers of digital telephone network interfaces, where reliable clock synchronization is critical. because the circuitry is internal, board designers do not have to add expensive or custom circuitry to support these types of environments. the ML53812-2 also includes an 8-channel stream-to-stream switch to connect one ct bus data stream to another at the same or different data rates. this type of connection makes it possible for ct bus compat- ible devices (such as scbus and mvip-90) to efficiently exchange data even though they operate at differ- ent rates. this stream switch enables switching between any of the 32 ct bus data streams operating at 2, 4, or 8 mb/s. depending upon the data stream rates, the stream switch provides a minimum of 256 and a maximum of 1024 unidirectional time slot connections. stream switches in other ML53812-2 devices, within a system, may be used simultaneously to increase switching capability. 5.3 test access port the current version of the ML53812-2 does not support ieee 1149.1 boundary scan. the test access port on the ML53812-2 passes tdi through to tdo when tms and trst_n are both high which simplifiers the transition to eventual boundary scan support. drive tms and trst_n both low for normal opera- tion. 5.4 pin continuity test for normal operation, the test pin is driven low. when the test pin is high, all pins except vdd, vss, nc, apll_pc, apll_vco, tms, tck, trst_n, tdi, tdo, test are sequentially "nanded" with ale and output on tdo. this test allows each input pin to be toggled and a corresponding output to be observed on the tdo pin to verify the proper connection of the ML53812-2 to a printed circuit board. 5.5 analog pll test for normal operation, the apll_test pin is driven low. 5.6 microprocessor interface both intel and motorola microprocessor bus interfaces are supported. drive i_n (m) low for intel mode and high for motorola mode. multiplexed addresses are latched on the falling edge of ale (as). if mul- tiplexed address is not used, drive ale (as) high. multiplexed address and data must be connected to both a_ and d_ pins.
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 9 oki semiconductor 5.7 analog pll the analog pll is used to create an internal 131.072 mhz clock locked to one of several reference fre- quencies. the analog pll reference signal is input on the apll_clkref pin and should be a stable clock typically 25 ppm. an external loop filter is required (see figure 3 ). 5.8 slave pll the slave pll is used to generate all of the internal timing for the ML53812-2. even when the ml53812- 2 is enabled as master, the slave pll is still in operation. the slave pll is a fast tracking digital pll oper- ating at 131.072 mhz. the slave pll can be configured to lock to one of the following sources: ? ct_c8_a and ct_frame_a ? ct_c8_b and ct_frame_b ? sclk and fr_comp ? c2 and fr_comp ? l_clk_0 and l_fs_0 ? l_clk_1 and l_fs_1 5.9 master pll the master pll is used to generate timing for the ct bus. the master pll is a digital pll operating at 131.072 mhz. when operating as primary master the pll can lock to one of eight local network refer- ences, or one of two ct bus network references. these reference signals may be 8 khz, 1.536 mhz, 1.544 mhz or 2.048 mhz. when operating as secondary master the pll locks to the primary ct bus master. the master pll can be configured to automatically switch from secondary to primary in the event of a ct bus timing error. the master pll can be configured to drive either the ct bus "a" or "b" signals as well as all of the com- patibility clocks defined in the h.100/h.110 specifications. when operating as the primary master, the pll provides jitter attenuation with a cut-off frequency of 1.25 hz and a roll-off of 20db per decade. when operating as the secondary master, the pll is fast track- ing. when operating as the primary master, the pll has a lock range of 488 ppm (minus the tolerance of apll_clkref source). the maximum lock time is 3s. holdover stability is 0.06 ppm, resulting in a frame slip rate of 42/day, assuming no drift in apll_clkref source, exceeding the 62411 stratum 3 requirement of 255/day. during normal operation new holdover values are updated at 128ms intervals. ci 0.01 f r2 100 w r1 19 k w apll_pc apll_vco apll_vss figure 3. analog pll loop filter
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 10 oki semiconductor to make an mtie compliant reference switch, enable "condition master pll reference", select the "mas- ter pll reference", and configure the "master pll mode " to normal.the master pll will be locked to the selected reference. the following sequence will produce an mtie-compliant reference switch: 1. change the "master pll mode" from normal to holdover. the master pll can also be configured to make this change automatically in the event of a master pll error. 2. change the "master pll reference select" to the new reference, or change the reference source of ct_netref. 3. change the "master pll mode" back to normal. 5.10 reference master ct_netref_1 and ct_netref_2 can be independently configured to output a reference signal to the ct bus selected from one of eight local network reference inputs. the local network references can be passed through or divided by 192, 193, or 256. 5.11 local clock and frame sync two sets of local clock and frame sync are provided. a variety of clock frequencies, polarities, and fram- ing formats may be selected to allow "glue less" local port interfacing. each set of local clock and frame sync may be configured separately. the frequency selection is independent of the local stream rate. 5.12 local streams the local streams consist of up to eight serial input ports and eight serial output ports, defined as two groups of 128 time-slots. each group can be independently configured to operate as four 2 mb/s streams, two 4 mb/s streams, or one 8 mb/s stream. mtie specifications ML53812-2 62411 stratum 3 and 4e mtie during rearrangement 100 ns 1 s phase change slope 81 ns / 1.326 ms 81 ns / 1.326 ms local stream time slot to channel mapping local stream 8mb/s stream rate time slot 127:0 4mb/s stream rate time slot 63:0 2mb/s stream rate time slot 31:0 l_si_0,l_so_0 channel 127:0 channel 63:0 channel 31:0 l_si_1,l_so_1 - channel 127:64 channel 63:32 l_si_2,l_so_2 - - channel 95:64 l_si_3,l_so_3 - - channel 127:96 l_si_4,l_so_4 channel 255:128 channel 191:128 channel 159:128 l_si_5,l_so_5 - channel 255:192 channel 191:160 l_si_6,l_so_6 - - channel 223:192 l_si_7,l_so_7 - - channel 255:224
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 11 oki semiconductor 5.13 ct bus streams connection to all 32 ct bus streams is supported without restriction. the upper 16 streams run at 8mb/s while the lower 16 may be configured, in groups of four, to operate at 8mb/s, 4mb/s, or 2mb/s. 5.14 ct_d disable the user may disable all ct_d output streams in the event of a bus timing error. when enabled, an error on the slave pll reference source causes the ct_d streams to be tri-stated until an entire frame time without errors has passed. the ct_d_disable signal is provided to link multiple ML53812-2 devices. 5.15 diagnostic mode diagnostic mode tri-states all ct bus signals while internally looping-back ct bus outputs to inputs. this mode allows a printed circuit board containing the ML53812-2 to be thoroughly tested without causing ct bus errors. 5.16 interrupts the ML53812-2 supports the following interrupt sources: ? ct bus a error ? ct bus b error ct bus a (ct bus b) error is detected when ct_c8_a (ct_c8_b) rising edge does not occur within 35 ns of the expected time, relative to the previous period (see figure 4 ) or when ct_frame_a_n (ct_frame_b_n) low does not occur when expected. (see ectf h.100/h.110 specifications for details on ct_c8_(a/b) and ct_frame_(a/b)_n signal timing.) ? scbus error scbus error is detected when sclk does not transition at close to the expected frequency (c_[25:24] determines the expected frequency) or fr_comp_n low does not occur when expected. (see ectf h.100/h.110 specifications for details on sclk, sclkx2, and fr_comp_n signal timing.) ? mvip error mvip error is detected when c2 does not transition at close to 2 mhz, or fr_comp_n low does not occur when expected. (see ectf h.100/h.110 specifications for details on c2 and fr_comp_n sig- nal timing). ? master pll out of lock error master pll error is detected when the master pll is not locked to the selected reference defined by c_[43:40]. ? frame boundary frame boundary interrupt is not an error condition, and occurs when the internal state machine crosses a frame boundary. ? gpio gpio interrupt occurs when one or more of the gpio inputs match the programmed latch polarity, defined by c_[167:136].
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 12 oki semiconductor the interrupts are both globally and individually maskable, and are signaled to the processor via the int pin (pin 10). the int pin can be configured to operate as either push-pull or open drain, and its polarity (active high or active low) is also selectable. all of these interrupt latches have an individual enable/clear register and an individual interrupt mask register associated with them. 5.17 gpio ports four general purpose input/output ports are provided. the ports may be individually configured to a variety of modes and can also be used as interrupt sources. possible uses of the gpio ports would be con- trolling h.100/h.110 termination switches or implementing the scbus clkfail signal. 5.18 message channel the ML53812-2 provides a complete interface between the ct_mc ct bus signal and a local hdlc con- troller. this includes generation of mc_clk as well as buffering of mc_txd and mc_rxd. figure 4. ct_c8_a and ct_c8_b error detection ct_c8_(a/b) expected delay (approx. 125 ns) late allowance (35 ns) rising edge of ct_c8 occurring after this limit will trigger an interrupt (if enabled).
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 13 oki semiconductor 6.0 registers 6.1 microprocessor address map with direct parallel access disabled (c_[96] = 0) (default) a_[2:0] register 7h reserved 6h data register 2 (dr_2) 5h data register 1 (dr_1) 4h data register 0 (dr_0) 3h reserved 2h address register 1 (ar_1) 1h address register 0 (ar_0) 0h command/status register with direct parallel access enabled (c_[96] = 1) a_[9:0] register 3ffh:300h direct receive switch parallel access ch. 255:0 2ffh:200h direct transmit switch parallel access ch. 255:0 1ffh:008h reserved 007h reserved 006h data register 2 (dr_2) 005h data register 1 (dr_1) 004h data register 0 (dr_0) 003h reserved 002h address register 1 (ar_1) 001h address register 0 (ar_0) 000h command/status register
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 14 oki semiconductor 6.2 command/status register note: for "reads" that do not require synchronization (all "reads" except in-direct parallel access read) it is not necessary to set this bit. the data registers can be read immediately after writing the address register. d_[7:0] definition 0 busy (read only) 1 read command (write only) 2 write command (write only) 3 terminate command (write only) 4 reserved 5 reserved 6 reserved 7 reset (read/write) busy (d_0) (read only) this bit is set ("1") when a command that requires synchronization with the ML53812-2's internal state machine has been initiat ed, and cleared ("0") when the command has been completed. for commands that do not require synchronization this bit is always clear ("0"). the following commands require synchronization: ? routing memory write command ? in-direct parallel access read or write command read (d_1) (write only) setting this bit ("1") initiates a synchronized read of the register pointed to by the address register. when the busy bit is c lear ("0"), the contents of the register to be read are available by reading the data register. it is not necessary to clear ("0") this bit after it has be en set ("1"). write (d_2) (write only) setting this bit ("1") initiates a write of the register pointed to by the address register. it is not necessary to clear ("0") this bit after it has been set ("1"). terminate (d_3) (write only) setting this bit ("1") terminates a command that requires synchronization with the ML53812-2's internal state machine. the comm and in process is completed asynchronously and the busy bit is cleared. it is not necessary to clear ("0") this bit after it has been set ("1"). reset (d_7) (read/write) setting this bit ("1") resets the ML53812-2 and initializes the configuration and routing registers. this command is analogous to the function of the reset pin. clearing this bit ("0") returns the ML53812-2 to normal operation, ready to be configured.
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 15 oki semiconductor 6.3 internal address map [1] [2] 1. ar is the concatenation of ar_1 and ar_0. 2. all other locations reserved (read-back = 00, write has no effect). ar register 0014h:0000h configuration 00ffh:00fch device id 1007h:1000h stream switch routing ch. 7:0 20ffh:2000h transmit switch routing ch. 255:0 30ffh:3000h receive switch routing ch. 255:0 40ffh:4000h indirect transmit switch parallel access ch. 255:0 50ffh:5000h indirect receive switch parallel access ch. 255:0
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 16 oki semiconductor 6.4 configuration registers note: all "reserved" configuration registers should be written "0". configuration register byte 0, ar = 0000h dr_0 c definition 0 0 diagnostic mode 1 1 test mode 2 2 apll power-down mode 3 3 apll bypass mode [7:4] [7:4] apll clkref frequency [3:0] diagnostic mode (c_ [0]) (read/write) set to 0 for normal operation 0 ? diagnostic mode disabled 1 ? diagnostic mode enabled (default) test mode (c_ [1]) (read/write) enables testing with the slave dpll bypassed. set to 0 for normal operation. 0 ? test mode disabled (default) 1 ? test mode enabled apll power-down mode (c_ [2]) (read/write) powers down analog pll, resets apll charge pump. set to 0 for normal operation. 0 ? apll power-down mode disabled 1 ? apll power-down mode enabled (default) apll bypass mode (c_ [3]) (read/write) apll bypass used during simulation and testing. set to 0 for normal operation. 0 ? apll bypass mode disabled 1 ? apll bypass mode enabled (default) apll clkref frequency [3:0] (c_ [7:4]) (read/write) put apll in power-down (c_[2] = 1) when changing apll clkref frequency. 0h ? 65.536 mhz (32 x 2.048 mhz) (default) 1h ? 49.152 mhz (24 x 2.048 mhz) 2h ? 32.768 mhz (16 x 2.048 mhz) 3h ? 16.384 mhz (8 x 2.048 mhz) 4h ? 8.192 mhz (4 x 2.048 mhz) 5h ? 4.096 mhz (2 x 2.048 mhz) 6h ? 2.048 mhz 7h - fh ? reserved
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 17 oki semiconductor configuration register byte 1, ar = 0001h dr_0 c definition [1:0] [9:8] slave bus mode [1:0] 2 10 slave local timing source select 3 11 advance slave pll timing 4 12 slave ct manual/auto mode 5 13 slave ct a/b select 6 14 slave ct a/b read-back 7 15 reserved slave bus mode [1:0] (c_ [9:8]) (read/write) [1] 1. when local slave mode is selected, l_clk frequency, polarity and output enable, and l_fs polarity, position and output enable must be configured accordingly. 00 ? ct bus - slave to ct_c8 & ct_frame (see slave ct a/b select) (default) 01 ? scbus - slave to sclk & fr_comp 10 ? mvip - slave to c2 & fr_comp 11 ? local - slave to l_clk & l_fs (see slave local timing source select) slave local timing source select (c_ [10]) (read/write) 0 ? l_clk_0, l_fs_0 (default) 1 ? l_clk_1, l_fs_1 advance slave pll timing (c_ [11]) (read/write) the slave pll timing may be advanced one 7.6 ns period to compensate for delay. set to 0 for normal operation. 0 ? advance slave pll timing disabled (default) 1 ? advance slave pll timing enabled slave ct manual/auto mode (c_ [12]) (read/write) [1] 1. in auto mode, slave will only switch when an error exists on the current signal set and not on the other signal set. 0 ? slave ct manual mode (default) 1 ? slave ct auto mode slave ct a/b select (c_ [13]) (read/write) select signal set in manual mode then switch to auto. 0 ? ct a select (default) 1 ? ct b select slave ct a/b read-back (c_ [14]) (read only) 0 ? ct a selected 1 ? ct b selected
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 18 oki semiconductor configuration register byte 2, ar = 0002h dr_0 c definition 0 16 master ct enable 1 17 master ct a/b select 2 18 reserved 3 19 advance master pll timing 4 20 master manual/auto mode 5 21 master primary/secondary select 6 22 master primary/secondary read-back 7 23 reserved master ct enable (c_ [16]) (read/write) enables the master pll to drive the ct bus. 0 ? master disabled (default) 1 ? master enabled master ct a/b select (c_ [17]) (read/write) [1] 1. when in secondary master mode, the signal set (a or b) not selected here is used as the reference. selects the signal set driven by the master pll. 0 ? ct_c8_a & ct_frame_a (default) 1 ? ct_c8_b & ct_frame_b advance master pll timing (c_ [19]) (read/write) when operating as secondary master, the master pll timing may be advanced one 7.6 ns clock period to compensate for delay. set to 0 for normal operation. 0 ? advance master pll timing disabled (default) 1 ? advance master pll timing enabled master manual/auto mode (c_ [20]) (read/write) [1] 1. master auto mode allows secondary master to become primary if an error occurs on the reference signal set. to switch back to secondary master it is necessary to go into manual mode. 0 ? master manual mode (default) 1 ? master auto mode master primary/secondary select (c_ [21]) (read/write) 0 ? primary master select (default) 1 ? secondary master select master primary/secondary read-back (c_ [22]) (read only) 0 ? primary master selected 1 ? secondary master selected
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 19 oki semiconductor configuration register byte 3, ar = 0003h dr_0 c definition [1:0] [25:24] scbus sclk frequency [1:0] 2 26 scbus master enable - sclk, sclkx2 & fr_comp 3 27 reserved 4 28 mvip-90 master enable - c2, c4 & fr_comp 5 29 h-mvip master enable - c2, c4, c16 & fr_comp 6 30 reserved 7 31 reserved scbus sclk frequency [1:0] (c_ [25:24]) (read/write) 00 ? 2.048 mhz (default) 01 ? 4.096 mhz 10 ? 8.192 mhz 11 ? reserved scbus master enable (c_ [26]) (read/write) when enabled as primary master, this register enables the sclk, sclkx2 & fr_comp signals to be driven. 0 ? scbus master disabled (default) 1 ? scbus master enabled mvip-90 master enable (c_ [28]) (read/write) when enabled as primary master, this register enables the c2, c4 & fr_comp signals to be driven. 0 ? mvip-90 master disabled (default) 1 ? mvip-90 master enabled h-mvip master enable (c_ [29]) (read/write) when enabled as primary master, this register enables the c2, c4, c16 & fr_comp signals to be driven. 0 ? h-mvip master disabled (default) 1 ? h-mvip master enabled
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 20 oki semiconductor configuration register byte 4, ar = 0004h dr_0 c definition [2:0] [34:32] master pll mode [2:0] 3 35 reserved [5:4] [37:36] master pll mode read-back [1:0] 6 38 condition master pll reference 7 39 reserved master pll mode [2:0] (c_ [34:32]) (read/write) [1] 1. master pll error occurs when the master pll is out of lock with its reference signal. it is necessary to manually select "nor mal" to go back to normal operation after an auto switch has occurred. 000 ? normal (default) 001 ? reserved 010 ? holdover 011 ? free run 100 ? reserved 101 ? reserved 110 ? auto normal to holdover switch on master pll error 111 ? auto normal to free run switch on master pll error master pll mode read-back [1:0] (c_ [37:36]) (read only) 00 ? normal 01 ? reserved 10 ? holdover 11 ? free run condition master pll reference (c_ [38]) (read/write) when enabled, conditions a change in references for mtie compatibility. 0 ? condition master pll reference disabled (default) 1 ? condition master pll reference enabled
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 21 oki semiconductor configuration register byte 5, ar = 0005h dr_0 c definition [3:0] [43:40] master pll reference select [3:0] 4 44 reserved [6:5] [46:45] master pll reference frequency [1:0] 7 47 reserved master pll reference select [3:0] (c_ [43:40]) (read/write) 0h ? none (default) 1h ? reserved 2h ? reserved 3h ? reserved 4h ? reserved 5h ? reserved 6h ? ct_netref_1 7h ? ct_netref_2 8h ? l_netref_0 9h ? l_netref_1 ah ? l_netref_2 bh ? l_netref_3 ch ? l_netref_4 dh ? l_netref_5 eh ? l_netref_6 fh ? l_netref_7 master pll reference frequency [1:0] (c_ [46:45]) (read/write) 00 ? 8 khz (default) 01 ? 1.536 mhz 10 ? 1.544 mhz 11 ? 2.048 mhz
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 22 oki semiconductor configuration register byte 6, ar = 0006h dr_0 c definition [3:0] [51:48] ct_netref_1 source select [3:0] 4 52 reserved [6:5] [54:53] ct_netref_1 divider [1:0] 7 55 ct_netref_1 output enable ct_netref_1 source select [3:0] (c_ [51:48]) (read/write) 0h ? none (default) 1h ? reserved 2h ? reserved 3h ? reserved 4h ? reserved 5h ? reserved 6h ? reserved 7h ? reserved 8h ? l_netref_0 9h ? l_netref_1 ah ? l_netref_2 bh ? l_netref_3 ch ? l_netref_4 dh ? l_netref_5 eh ? l_netref_6 fh ? l_netref_7 ct_netref_1 divider [1:0] (c_ [54:53]) (read/write) 00 ? divide source by 1 (default) 01 ? divide source by 192 10 ? divide source by 193 11 ? divide source by 256 ct_netref_1 output enable (c_ [55]) (read/write) 0 ? ct_netref_1 output tri-stated (default) 1 ? ct_netref_1 output enabled
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 23 oki semiconductor configuration register byte 7, ar = 0007h dr_0 c definition [3:0] [59:56] ct_netref_2 source select [3:0] 4 60 reserved [6:5] [62:61] ct_netref_2 divider [1:0] 7 63 ct_netref_2 output enable ct_netref_2 source select [3:0] (c_ [59:56]) (read/write) 0h ? none (default) 1h ? reserved 2h ? reserved 3h ? reserved 4h ? reserved 5h ? reserved 6h ? reserved 7h ? reserved 8h ? l_netref_0 9h ? l_netref_1 ah ? l_netref_2 bh ? l_netref_3 ch ? l_netref_4 dh ? l_netref_5 eh ? l_netref_6 fh ? l_netref_7 ct_netref_2 divider [1:0] (c_ [62:61]) (read/write) 00 ? divide source by 1 (default) 01 ? divide source by 192 10 ? divide source by 193 11 ? divide source by 256 ct_netref_2 output enable (c_ [63]) (read/write) 0 ? ct_netref_2 output tri-stated (default) 1 ? ct_netref_2 output enabled
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 24 oki semiconductor configuration register byte 8, ar = 0008h dr_0 c definition 0 64 l_clk_0, l_fs_0 output enable 1 65 l_clk_1, l_fs_1 output enable 2 66 ct_d_ output enable mode 3 67 ct_d_disable output enable 4 68 ct_d_disable 5 69 ct_d_disable on input 6 70 ct_d_disable on error 7 71 ct_d_disable read-back l_clk_0, l_fs_0 output enable (c_ [64]) (read/write) 0 ? l_clk_0, l_fs_0 output tri-stated (default) 1 ? l_clk_0, l_fs_0 output enabled l_clk_1, l_fs_1 output enable (c_ [65]) (read/write) 0 ? l_clk_1, l_fs_1 output tri-stated (default) 1 ? l_clk_1, l_fs_1 output enabled ct_d_ output enable mode (c_ [66]) (read/write) 0 ? ct_d_[31:0] output tri-stated before bit cell boundary - based on h.100/h.110 (default) 1 ? ct_d_[31:0] output tri-stated at bit cell boundary ct_d_disable output enable (c_ [67]) (read/write) 0 ? ct_d_disable pin output tri-stated (default) 1 ? ct_d_disable pin output enabled ct_d_disable (c_ [68]) (read/write) 0 ? ct_d_ outputs enabled (default) 1 ? ct_d_ outputs disabled ct_d_disable on input (c_ [69]) (read/write) 0 ? ct_d_disable on input disabled (default) 1 ? ct_d_disable on input enabled ct_d_disable on error (c_ [70]) (read/write) 0 ? ct_d_disable on error disabled (default) 1 ? ct_d_disable on error enabled ct_d_disable read-back (c_ [71]) (read only) 0 ? ct_d_ outputs enabled 1 ? ct_d_ outputs disabled
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 25 oki semiconductor configuration register byte 9, ar = 0009h dr_0 c definition [1:0] [73:72] l_si_[3:0], l_so_[3:0] stream rate [1:0] [3:2] [75:74] l_clk_0 frequency [1:0] 4 76 l_clk_0 polarity 5 77 l_fs_0 polarity [7:6] [79:78] l_fs_0 position [1:0] l_si_[3:0], l_so_[3:0] stream rate [1:0] (c_ [73:72]) (read/write) 00 ? 2.048 mb/s (l_si_[3:0], l_so_[3:0]) (default) 01 ? 4.096 mb/s (l_si_[1:0], l_so_[1:0]) 10 ? 8.192 mb/s (l_si_[0], l_so_[0]) 11 ? reserved l_clk_0 frequency [1:0] (c_ [75:74]) (read/write) [1] 1. note: the l_clk_0 frequency need not match the l_si and l_so stream frequencies, neither need it match the ct_c8 frequency wh en configured as slave-to-ct. 00 ? 2.048 mhz (default) 01 ? 4.096 mhz 10 ? 8.192 mhz 11 ? 16.384 mhz l_clk_0 polarity (c_ [76]) (read/write) 0 ? l_clk_0 non-inverted (default) 1 ? l_clk_0 inverted l_fs_0 polarity (c_ [77]) (read/write) 0 ? l_fs_0 non-inverted (default) 1 ? l_fs_0 inverted l_fs_0 position [1:0] (c_ [79:78]) (read/write) 00 ? early - l_fs_0 occurs during the last l_clk_0 period of the frame (default) 01 ? straddle - l_fs_0 straddles the frame boundary 10 ? late - l_fs_0 occurs during the first l_clk_0 period of the frame 11 ? reserved
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 26 oki semiconductor configuration register byte 10, ar = 000ah dr_0 c definition [1:0] [81:80] l_si_[7:4], l_so_[7:4] stream rate [1:0] [3:2] [83:82] l_clk_1 frequency [1:0] 4 84 l_clk_1 polarity 5 85 l_fs_1 polarity [7:6] [87:86] l_fs_1 position [1:0] l_si_[7:4], l_so_[7:4] stream rate [1:0] (c_ [81:80]) (read/write) 00 ? 2.048 mb/s (l_si_[7:4], l_so_[7:4]) (default) 01 ? 4.096 mb/s (l_si_[5:4], l_so_[5:4]) 10 ? 8.192 mb/s (l_si_[4], l_so_[4]) 11 ? reserved l_clk_1 frequency [1:0] (c_ [83:82]) (read/write) [1] 1. note: the l_clk_1 frequency need not match the l_si and l_so stream frequencies, neither need it match the ct_c8 frequency wh en configured as slave-to-ct. 00 ? 2.048 mhz (default) 01 ? 4.096 mhz 10 ? 8.192 mhz 11 ? 16.384 mhz l_clk_1 polarity (c_ [84]) (read/write) 0 ? l_clk_1 non-inverted (default) 1 ? l_clk_1 inverted l_fs_1 polarity (c_ [85]) (read/write) 0 ? l_fs_1 non-inverted (default) 1 ? l_fs_1 inverted l_fs_1 position [1:0] (c_ [87:86]) (read/write) 00 ? early - l_fs_1 occurs during the last l_clk_1 period of the frame (default) 01 ? straddle - l_fs_1 straddles the frame boundary 10 ? late - l_fs_1 occurs during the first l_clk_1 period of the frame 11 ? reserved
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 27 oki semiconductor configuration register byte 11, ar = 000bh dr_0 c definition [1:0] [89:88] ct_d_[3:0] data stream rate [1:0] [3:2] [91:90] ct_d_[7:4] data stream rate [1:0] [5:4] [93:92] ct_d_[11:8] data stream rate [1:0] [7:6] [95:94] ct_d_[15:12] data stream rate [1:0] ct_d_[3:0] data stream rate [1:0] (c_ [89:88]) (read/write) 00 ? 2.048 mb/s 01 ? 4.096 mb/s 10 ? 8.192 mb/s (default) 11 ? reserved ct_d_[7:4] data stream rate [1:0] (c_ [91:90]) (read/write) 00 ? 2.048 mb/s 01 ? 4.096 mb/s 10 ? 8.192 mb/s (default) 11 ? reserved ct_d_[11:8] data stream rate [1:0] (c_ [93:92]) (read/write) 00 ? 2.048 mb/s 01 ? 4.096 mb/s 10 ? 8.192 mb/s (default) 11 ? reserved ct_d_[15:12] data stream rate [1:0] (c_ [95:94]) (read/write) 00 ? 2.048 mb/s 01 ? 4.096 mb/s 10 ? 8.192 mb/s (default) 11 ? reserved
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 28 oki semiconductor configuration register byte 12, ar = 000ch dr_0 c definition 0 96 direct parallel access enable 1 97 microprocessor watchdog enable 2 98 apll clock watchdog enable 3 99 reserved 4 100 message channel registered txd enable 5 101 message channel output disable 6 102 reserved 7 103 reserved direct parallel access enable (c_ [96]) (read/write) 0 ? direct parallel access disabled (default) 1 ? direct parallel access enabled microprocessor watchdog enable (c_ [97]) (read/write) when enabled, the ML53812-2 enters into reset after the analog pll clocks for 256ms ( 50%). each time c_[97] is cleared (0) and then set (1), the microprocessor watchdog count is reset. 0 ? microprocessor watchdog disabled (default) 1 ? microprocessor watchdog enabled apll clock watchdog enable (c_ [98]) (read/write) when enabled, c_[98] will read back as being set (1) until the analog pll clocks for 125 s ( 50%), then will read back as bei ng cleared (0). each time c_[98] is cleared (0) and then set (1), the clock watchdog count is reset. 0 ? apll clock watchdog disabled (default) 1 ? apll clock watchdog enabled message channel registered txd enable (c_ [100]) (read/write) 0 ? mc_txd passed though to ct_mc (default) 1 ? mc_txd registered to ct_mc on rising edge of mc_clk message channel output disable with loop-back (c_ [101]) (read/write) when ct_mc output is disabled, the local message channel circuitry can be tested without disturbing the ct bus. 0 ? ct_mc output enabled (default) 1 ? ct_mc output tri-stated, mc_txd looped back to mc_rxd
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 29 oki semiconductor configuration register byte 13, ar = 000dh dr_0 c definition 0 104 int polarity 1 105 int mask 2 106 int output driver configuration 3 107 int 4 108 reserved 5 109 reserved 6 110 reserved 7 111 reserved int polarity (c_ [104]) (read/write) 0 ? int active low (default) 1 ? int active high int mask (c_ [105]) (read/write) 0 ? int unmasked 1 ? int masked (default) int output driver configuration (c_ [106]) (read/write) 0 ? open drain (default) 1 ? push-pull int (c_ [107]) (read only) this register is the logical or of all unmasked interrupt sources. 0 ? all unmasked interrupts false 1 ? any unmasked interrupt true
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 30 oki semiconductor configuration register byte 14, ar = 000eh [1] 1. masking an interrupt disables that interrupt from being ored together with other interrupts to the int pin. the state of the latches are accessible while masked (polling mode). dr_0 c definition 0 112 ct bus a error interrupt mask 1 113 ct bus b error interrupt mask 2 114 scbus error interrupt mask 3 115 mvip error interrupt mask 4 116 master pll error interrupt mask 5 117 frame boundary interrupt mask 6 118 reserved 7 119 reserved ct bus a error interrupt mask (c_ [112]) (read/write) 0 ? ct bus a error interrupt unmasked 1 ? ct bus a error interrupt masked (default) ct bus b error interrupt mask (c_ [113]) (read/write) 0 ? ct bus b error interrupt unmasked 1 ? ct bus b error interrupt masked (default) scbus error interrupt mask (c_ [114]) (read/write) 0 ? scbus error interrupt unmasked 1 ? scbus error interrupt masked (default) mvip error interrupt mask (c_ [115]) (read/write) 0 ? mvip error interrupt unmasked 1 ? mvip error interrupt masked (default) master pll error interrupt mask (c_ [116]) (read/write) 0 ? master pll error interrupt unmasked 1 ? master pll error interrupt masked (default) frame boundary interrupt mask (c_ [117]) (read/write) 0 ? frame boundary interrupt unmasked 1 ? frame boundary interrupt masked (default)
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 31 oki semiconductor configuration register byte 15, ar = 000fh dr_0 c definition 0 120 ct bus a error latch clear 1 121 ct bus b error latch clear 2 122 scbus error latch clear 3 123 mvip error latch clear 4 124 master pll error latch clear 5 125 frame boundary latch clear 6 126 reserved 7 127 reserved ct bus a error latch clear (c_ [120]) (read/write) 0 ? ct bus a error latch enabled 1 ? ct bus a error latch held clear (default) ct bus b error latch clear (c_ [121]) (read/write) 0 ? ct bus b error latch enabled 1 ? ct bus b error latch held clear (default) scbus error latch clear (c_ [122]) (read/write) 0 ? scbus error latch enabled 1 ? scbus error latch held clear (default) mvip error latch clear (c_ [123]) (read/write) 0 ? mvip error latch enabled 1 ? mvip error latch held clear (default) master pll error latch clear (c_ [124]) (read/write) 0 ? master pll error latch enabled 1 ? master pll error latch held clear (default) frame boundary latch clear (c_ [125]) (read/write) 0 ? frame boundary latch enabled 1 ? frame boundary latch held clear (default)
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 32 oki semiconductor configuration register byte 16, ar = 0010h dr_0 c definition 0 128 ct bus a error latch 1 129 ct bus b error latch 2 130 scbus error latch 3 131 mvip error latch 4 132 master pll error latch 5 133 frame boundary latch 6 134 reserved 7 135 reserved ct bus a error latch (c_ [128]) (read only) 0 ? ct bus a error latch false 1 ? ct bus a error latch true ct bus b error latch (c_ [129]) (read only) 0 ? ct bus b error latch false 1 ? ct bus b error latch true scbus error latch (c_ [130]) (read only) 0 ? scbus error latch false 1 ? scbus error latch true mvip error latch (c_ [131]) (read only) 0 ? mvip error latch false 1 ? mvip error latch true master pll error latch (c_ [132]) (read only) 0 ? master pll error latch false 1 ? master pll error latch true frame boundary latch (c_ [133]) (read only) 0 ? frame boundary latch false 1 ? frame boundary latch true
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 33 oki semiconductor configuration register byte 17, ar = 0011h dr_0 c definition 0 136 gpio_0 input 1 137 gpio_0 output 2 138 gpio_0 output enable 3 139 gpio_0 output driver configuration 4 140 gpio _0 latch polarity 5 141 gpio _0 interrupt mask 6 142 gpio _0 latch clear 7 143 gpio _0 latch gpio_0 input (c_ [136]) (read only) 0 ? gpio_0 input = 0 1 ? gpio_0 input = 1 gpio_0 output (c_ [137]) (read/write) 0 ? gpio_0 output = 0 (default) 1 ? gpio_0 output = 1 gpio_0 output enable (c_ [138]) (read/write) 0 ? gpio_0 output tri-stated (default) 1 ? gpio_0 output enabled gpio_0 output driver configuration (c_ [139]) (read/write) 0 ? open drain (default) 1 ? push-pull gpio _0 latch polarity (c_ [140]) (read/write) 0 ? gpio _0 latch set when gpio_0 input = 0 (default) 1 ? gpio _0 latch set when gpio_0 input = 1 gpio _0 interrupt mask (c_ [141]) (read/write) 0 ? gpio _0 interrupt unmasked 1 ? gpio _0 interrupt masked (default) gpio _0 latch clear (c_ [142]) (read/write) 0 ? gpio _0 latch enabled 1 ? gpio _0 latch held clear (default) gpio _0 latch (c_ [143]) (read only) 0 ? gpio _0 latch false 1 ? gpio _0 latch true
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 34 oki semiconductor configuration register byte 18, ar = 0012h dr_0 c definition 0 144 gpio_1 input 1 145 gpio_1 output 2 146 gpio_1 output enable 3 147 gpio_1 output driver configuration 4 148 gpio _1 latch polarity 5 149 gpio _1 interrupt mask 6 150 gpio _1 latch clear 7 151 gpio _1 latch gpio_1 input (c_ [144]) (read only) 0 ? gpio_1 input = 0 1 ? gpio_1 input = 1 gpio_1 output (c_ [145]) (read/write) 0 ? gpio_1 output = 0 (default) 1 ? gpio_1 output = 1 gpio_1 output enable (c_ [146]) (read/write) 0 ? gpio_1 output tri-stated (default) 1 ? gpio_1 output enabled gpio_1 output driver configuration (c_ [147]) (read/write) 0 ? open drain (default) 1 ? push-pull gpio _1 latch polarity (c_ [148]) (read/write) 0 ? gpio _1 latch set when gpio_1 input = 0 (default) 1 ? gpio _1 latch set when gpio_1 input = 1 gpio _1 interrupt mask (c_ [149]) (read/write) 0 ? gpio _1 interrupt unmasked 1 ? gpio _1 interrupt masked (default) gpio _1 latch clear (c_ [150]) (read/write) 0 ? gpio _1 latch enabled 1 ? gpio _1 latch held clear (default) gpio _1 latch (c_ [151]) (read only) 0 ? gpio _1 latch false 1 ? gpio _1 latch true
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 35 oki semiconductor configuration register byte 19, ar = 0013h dr_0 c definition 0 152 gpio_2 input 1 153 gpio_2 output 2 154 gpio_2 output enable 3 155 gpio_2 output driver configuration 4 156 gpio _2 latch polarity 5 157 gpio _2 interrupt mask 6 158 gpio _2 latch clear 7 159 gpio _2 latch gpio_2 input (c_ [152]) (read only) 0 ? gpio_2 input = 0 1 ? gpio_2 input = 1 gpio_2 output (c_ [153]) (read/write) 0 ? gpio_2 output = 0 (default) 1 ? gpio_2 output = 1 gpio_2 output enable (c_ [154]) (read/write) 0 ? gpio_2 output tri-stated (default) 1 ? gpio_2 output enabled gpio_2 output driver configuration (c_ [155]) (read/write) 0 ? open drain (default) 1 ? push-pull gpio _2 latch polarity (c_ [156]) (read/write) 0 ? gpio _2 latch set when gpio_2 input = 0 (default) 1 ? gpio _2 latch set when gpio_2 input = 1 gpio _2 interrupt mask (c_ [157]) (read/write) 0 ? gpio _2 interrupt unmasked 1 ? gpio _2 interrupt masked (default) gpio _2 latch clear (c_ [158]) (read/write) 0 ? gpio _2 latch enabled 1 ? gpio _2 latch held clear (default) gpio _2 latch (c_ [159]) (read only) 0 ? gpio _2 latch false 1 ? gpio _2 latch true
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 36 oki semiconductor configuration register byte 20, ar = 0014h dr_0 c definition 0 160 gpio_3 input 1 161 gpio_3 output 2 162 gpio_3 output enable 3 163 gpio_3 output driver configuration 4 164 gpio _3 latch polarity 5 165 gpio _3 interrupt mask 6 166 gpio _3 latch clear 7 167 gpio _3 latch gpio_3 input (c_ [160]) (read only) 0 ? gpio_3 input = 0 1 ? gpio_3 input = 1 gpio_3 output (c_ [161]) (read/write) 0 ? gpio_3 output = 0 (default) 1 ? gpio_3 output = 1 gpio_3 output enable (c_ [162]) (read/write) 0 ? gpio_3 output tri-stated (default) 1 ? gpio_3 output enabled gpio_3 output driver configuration (c_ [163]) (read/write) 0 ? open drain (default) 1 ? push-pull gpio _3 latch polarity (c_ [164]) (read/write) 0 ? gpio _3 latch set when gpio_3 input = 0 (default) 1 ? gpio _3 latch set when gpio_3 input = 1 gpio _3 interrupt mask (c_ [165]) (read/write) 0 ? gpio _3 interrupt unmasked 1 ? gpio _3 interrupt masked (default) gpio _3 latch clear (c_ [166]) (read/write) 0 ? gpio _3 latch enabled 1 ? gpio _3 latch held clear (default) gpio _3 latch (c_ [167]) (read only) 0 ? gpio _3 latch false 1 ? gpio _3 latch true
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 37 oki semiconductor 6.5 device id registers (read only) ML53812-2 device id byte [3:0] = 20 8c 00 00h device id byte 3, ar = 00ffh dr_0 definition [7:4] version [3:0] [3:0] part number [15:12] device id byte 2, ar = 00feh dr_0 definition [7:0] part number [11:4] device id byte 1, ar = 00fdh dr_0 definition [7:4] part number [3:0] [3:0] manufacturer id [10:7] device id byte 0, ar = 00fch dr_0 definition [7:1] manufacturer id [6:0] 0 0 = device does not support boundary scan 1 = device supports boundary scan
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 38 oki semiconductor 6.6 stream switch routing registers, ar = 1007h:1000h (ch. 7:0) note: to ensure compatibility with possible future versions of this device, write 0 to all "reserved" bits in the routing registers. all "reserved" routing registers read-back "0". partition [1:0] (read/write) selects which time-slots are used when rate conversion is taking place. see the following table for a description of the partition function. dr_0 definition [4:0] input data stream [4:0] [7:5] reserved (write zero) input data stream [4:0] (read/write) 00h ? ct_d_[0] (default) 01h ? ct_d_[1] 02h ? ct_d_[2] ? ? ? ? 1eh ? ct_d_[30] 1fh ? ct_d_[31] dr_1 definition [4:0] output data stream [4:0] [6:5] reserved (write zero) 7 output enable output data stream [4:0] (read/write) 00h ? ct_d_[0] (default) 01h ? ct_d_[1] 02h ? ct_d_[2] ? ? ? ? 1eh ? ct_d_[30] 1fh ? ct_d_[31] output enable (read/write) 0 ? output disabled (default) 1 ? output enabled dr_2 definition [1:0] partition [1:0] [7:2] reserved (write zero)
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 39 oki semiconductor the stream switch provides a data stream-to-data stream connection capability. switching between any of the 32 ct bus data streams operating at 2, 4, or 8 mb/s is supported. eight stream switch channels are provided. individual time-slots are not tri-state controlled. buffering is done on single timeslots rather than entire frames. this trade-off complicates the connection matrix, but without this compromise it would not be practical to implement the stream switch. depending upon the data stream rates, the stream switch provides a minimum of 256 and a maximum of 1024 uni-directional timeslot connections. stream switches in other ML53812-2 devices in a system may be used simultaneously to increase switching capability. the output of the stream switch is multiplexed with the output of the transmit switch, with the transmit switch having priority. 6.7 stream switch connection mapping input data stream rate output data stream rate partition timeslot connection 2 mb/s 2 mb/s 0 0 to 1, 1 to 2, 2 to 3, , 31 to 0 4 mb/s 0 0 to 2, 1 to 4, 2 to 6, , 31 to 0 1 0 to 3, 1 to 5, 2 to 7, , 31 to 1 8 mb/s 0 0 to 4, 1 to 8, 2 to 12, , 31 to 0 1 0 to 5, 1 to 9, 2 to 13, , 31 to 1 2 0 to 6, 1 to 10, 2 to 14, , 31 to 2 3 0 to 7, 1 to 11, 2 to 15, , 31 to 3 4 mb/s 2 mb/s 0 0 to 1, 2 to 2, 4 to 3, , 62 to 0 1 1 to 1, 3 to 2, 5 to 3, , 63 to 0 4 mb/s 0 0 to 1, 1 to 2, 2 to 3, , 63 to 0 8 mb/s 0 0 to 2, 1 to 4, 2 to 6, , 63 to 0 1 0 to 3, 1 to 5, 2 to 7, , 63 to 1 8 mb/s 2 mb/s 0 0 to 1, 4 to 2, 8 to 3, , 124 to 0 1 1 to 1, 5 to 2, 9 to 3, , 125 to 0 2 2 to 1, 6 to 2, 10 to 3, , 126 to 0 3 3 to 1, 7 to 2, 11 to 3, , 127 to 0 4 mb/s 0 0 to 1, 2 to 2, 4 to 3, , 126 to 0 1 1 to 1, 3 to 2, 5 to 3, , 127 to 0 8 mb/s 0 0 to 1, 1 to 2, 2 to 3, , 127 to 0 frame boundary 12312412512612701234 ct_d time-slots @ 4mb/s 123 62 63 0 1 2 ct_d time-slots @ 2mb/s 30 31 0 1 ct_d time-slots @ 8mb/s figure 5. ct bus data stream switching
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 40 oki semiconductor the main application of the stream switch is to provide an inter-rate exchange highway allowing legacy bus devices operating at different rates to exchange data. a typical configuration of the stream switch using 2 switch channels and 3 streams to provide 32 full duplex connections between scbus (operating at 4 mhz) and mvip is outlined below. example: stream switch channel 0 is configured with ct_d_0 as the input data stream and the even time-slots (partition = 0) of ct_d_8 as the output data stream. stream switch channel 1 is configured with the odd timeslots (partition = 1) of ct_d_8 as the input data stream and ct_d_1 as the output data stream. 31 0 ct_d _1 (mvip) ct_d _8 (scbus) 63 ct_d _0 (mvip) 1 01 2 01234 figure 6. data stream switching example
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 41 oki semiconductor 6.8 transmit switch routing registers, ar = 20ffh:2000h (ch. 255:0) note: to ensure compatibility with subsequent versions of this device, write 0 to all "reserved" bits in the routing registers. all "reserved" routing registers read-back "0". note: internally all time-slots run at 8mb/s. to transmit on ct_d data streams running at a slower rate, use the following conversion: if ct_d data stream is operating at 4mb/s, transmit switch output time-slot = ct_d time-slot x 2. if ct_d data stream is operating at 2mb/s, transmit switch output time-slot = ct_d time-slot x 4. dr_0 definition [6:0] output time-slot 7 reserved (write zero) output time-slot [6:0] (read/write) selects the ct_d time-slot for transmit channel routing. 00h ? time-slot 0 (default) 01h ? time-slot 1 02h ? time-slot 2 ? ? ? ? 7eh ? time-slot 126 7fh ? time-slot 127 dr_1 definition [4:0] output data stream [6:5] reserved (write zero) 7 output enable output data stream [4:0] (read/write) selects the ct_d data stream for transmit channel routing. 00h ? ct_d_[0] (default) 01h ? ct_d_[1] 02h ? ct_d_[2] ? ? ? ? 1eh ? ct_d_[30] 1fh ? ct_d_[31] output enable (read/write) controls the output enable for the selected ct bus data stream and time-slot. 0 ? output disabled (default) 1 ? output enabled
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 42 oki semiconductor note: do not use minimum delay mode on channels using parallel data source. note: the receive switch output enable register does not have to be set to make this connection. note: the serial tdm data and the parallel access register share common registers within the transmit switch. therefore it is necessary to write to the parallel access register after the source is changed to parallel microprocessor data. dr_2 definition 0 delay 1 ct bus connect 2 source [7:3] reserved (write zero) delay (read/write) selects the switching delay mode. when set to constant, data is switched on frame boundaries resulting in a constant 1 frame d elay and allowing "bundling". when set to minimum, data is switched on 2mb/s timeslot boundaries reducing the delay through the switch for certai n combinations of input to output time-slots. 0 ? constant (default) 1 ? minimum ct bus connect enable (read/write) enables the switch to be used for ct bus to ct bus connection without externally connecting l_so to l_si. when enabled, the l_s i input is replaced by the corresponding l_so output. ct bus connect allows inter-operability switching to be provided by any unused transmit and r eceive switch pair. 0 ? ct bus connect disabled (default) 1 ? ct bus connect enabled source (read/write) selects the transmit channel data source. when set to 0, serial tdm data from l_si or l_so (see ct bus connect enable) is selec ted. when set to 1, the corresponding parallel access register is selected as the source of the transmit channel data. 0 ? serial tdm data (default) 1 ? parallel microprocessor data
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 43 oki semiconductor 6.9 receive switch routing registers, ar = 30ffh:3000h (ch. 255:0) note: to ensure compatibility with subsequent versions of this device, write 0 to all "reserved" bits in the routing registers. all "reserved" routing registers read-back "0". note: internally all time-slots run at 8mb/s. to receive from ct_d streams running at a slower rate, use the following conversion: if ct_d stream is operating at 4mb/s, receive switch input time-slot register = ct_d time-slot x 2 + 1. if ct_d stream is operating at 2mb/s, receive switch input time-slot register = ct_d time-slot x 4 + 3. dr_0 definition [6:0] input time-slot 7 reserved (write zero) input time-slot [6:0] (read/write) selects the ct_d time-slot for receive channel routing. 00h ? time-slot 0 (default) 01h ? time-slot 1 02h ? time-slot 2 ? ? ? ? 7eh ? time-slot 126 7fh ? time-slot 127 dr_1 definition [4:0] input data stream [6:5] reserved (write zero) 7 output enable input data stream [4:0] (read/write) selects the ct_d data stream for receive channel routing. 00h ? ct_d_[0] (default) 01h ? ct_d_[1] 02h ? ct_d_[2] ? ? ? ? 1eh ? ct_d_[30] 1fh ? ct_d_[31] output enable (read/write) controls the output enable for the channels local stream. 0 ? output disabled (default) 1 ? output enabled
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 44 oki semiconductor note: do not use minimum delay mode on channels using parallel data source. note: when local connect is enabled, the receive switch routing registers dr_0 and dr_1 are redefined as the 8 bits of the transmit channel number instead of the ct_d time-slot and stream as shown below: note: the serial tdm data and the parallel access register share common registers within the receive switch. therefore it is necessary to write to the parallel access register after the source is changed to parallel microprocessor data. dr_2 definition 0 delay 1 local connect 2 source [7:3] reserved (write zero) delay (read/write) selects the switching delay mode. when set to constant, data is switched on frame boundaries resulting in a constant 1 frame d elay and allowing "bundling". when set to minimum, data is switched on 2mb/s timeslot boundaries reducing the delay through the switch for certai n combinations of input to output time-slots. 0 ? constant (default) 1 ? minimum local connect enable (read/write) enables the receive switch to be used for local connection. when enabled, a transmit channel is connected to a receive channel without using the ct bus. 0 ? local connect disabled (default) 1 ? local connect enabled dr_0_[6:0] ? transmit channel bits [6:0] dr_1_[7] dr_1_[0] ? ? output enable transmit channel bit [7] source (read/write) selects the receive channel data source. when set to 0, serial tdm data from the ct bus data stream or transmit channel (see lo cal connect enable) is selected. when set to 1, the channels parallel access register is selected as the source of the receive channel data. 0 ? serial tdm data (default) 1 ? parallel microprocessor data
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 45 oki semiconductor note: when converted from parallel to serial, tdm data bit 1 is transmitted first. note: when converted from parallel to serial, tdm data bit 1 is transmitted first. 6.10 indirect transmit switch parallel access registers, ar = 40ffh:4000h (ch. 255:0) dr_0 definition [7:0] tdm data [1:8] tdm data [1:8] (read/write) writing to this register provides the transmit data when the transmit switch channel is configured to use parallel microprocess or data as its source (to ct_d). this register and the serial input buffer share common hardware, therefore this register must be written after the trans mit switch channel source is changed from serial tdm data to parallel microprocessor data. the transmit switch channel output buffer data obtained by reading the tdm data register. when the transmit switch channel is c onfigured to use serial tdm data as its source, the data from the local si channel can be monitored. when the transmit switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be monitored. 6.11 indirect receive switch parallel access registers, ar = 50ffh:5000h (ch. 255:0) dr_0 definition [7:0] tdm data [1:8] tdm data [1:8] (read/write) writing to this register provides the receive data when the receive switch channel is configured to use parallel microprocessor data as its source (to l_so). this register and the serial input buffer share common hardware, so this register must be written after the receive swit ch channel source is changed from serial tdm data to parallel microprocessor data. the receive switch channel output buffer data is obtained by reading the tdm data register. when the receive switch channel is configured to use serial tdm data as its source, the data from the ct_d stream and timeslot selected in the receive switch routing registers can be moni tored. when the receive switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be moni tored.
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 46 oki semiconductor 7.0 electrical specifications notes: 1. pci drivers meet the ac specifications for the pci 5v signaling environment. 2. pin capacitance: input pins = 6 pf, output pins = 9 pf, bi-directional pins = 10 pf. 7.1 absolute maximum ratings parameter symbol test conditions min max unit storage temperature t s -65 150 c power supply voltage v ps -0.3 4.6 v input voltage v i -0.3 6 v 7.2 recommended operating conditions parameter symbol test conditions min max unit ambient temperature t a -40 85 c supply voltage v dd 3.0 3.6 v 7.3 dc electrical characteristics parameter symbol test conditions min max unit core supply current i ddc v ddc = 3.6v 125 ma i/o supply current i ddo v ddo = 3.6v 140 ma analog pll supply current i dda v dda = 3.6v 10 ma input high voltage v ih 2.0 5.5 v input low voltage v il -0.5 0.8 v schmitt input high voltage v t+ 2.05 5.5 v schmitt input low voltage v t- -0.5 0.7 v schmitt input hysteresis voltage v hys 0.4 v output high voltage - pci v oh-pci i oh = -2 ma 2.4 v output low voltage - pci v ol-pci i ol = 6 ma 0.55 v output high voltage C 24ma v oh-24ma i oh = -24 ma 2.4 v output low voltage C 24ma v ol-24ma i ol = 24 ma 0.4 v output high voltage C 8ma v oh-8ma i oh = -8 ma 2.4 v output low voltage C 8ma v ol-8ma i ol = 8 ma 0.4 v output high voltage C 6ma v oh-6ma i oh = -6 ma 2.4 v output low voltage C 6ma v ol-6ma i ol = 6 ma 0.4 v 50 k pull-up current i p v pad = 0 v -15 -170 a i/o leakage current i li/o v i/o = v dd or v ss 10 a
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 47 oki semiconductor 7.4 ac electrical characteristics note: signals ending in _n are active low. microprocessor interface timing - intel bus mode, non-multiplexed address [1] [2] [3] 1. timing measured with 100 pf load on d_[7:0]. 2. write cycle may be controlled by cs_n or wr_n. 3. ale=1. parameter symbol min typ max unit cs_n setup to wr_n - t1 40 ns wr_n pulse width t2 40 ns a_[9:0] setup to wr_n (c_96=1) t3 5 ns a_[2:0] setup to wr_n - (c_96=0) t4 40 ns a_[9:0] hold from wr_n - t5 5 ns d_[7:0] setup to wr_n - t6 40 ns d_[7:0] hold from wr_n - t7 5 ns d_[7:0] float to valid delay from cs_n rd_n, and a_[9:0] t8 0 50 ns d_[7:0] valid to float delay from cs_n or rd_n t9 0 10 ns figure 7. microprocessor interface timing - intel bus mode, non-multiplexed address cs_n rd_n wr_n a_[9:0] d_[7:0] t1 t2 t4 t3 t5 t7 t6 t8 t9
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 48 oki semiconductor microprocessor interface timing - motorola bus mode, non-multiplexed address [1] [2] [3] 1. timing measured with 100 pf load on d_[7:0]. 2. write cycle may be controlled by cs_n or strb_n. 3. as=1. parameter symbol min typ max unit cs_n setup to strb_n - t1 40 ns strb_n pulse width t2 40 ns r/w_n setup to strb_n t3 5 ns r/w_n hold from strb_n - t4 5 ns a_[9:0] setup to strb_n (c_96=1) t5 5 ns a_[2:0] setup to strb_n - (c_96=0) t6 40 ns a_[9:0] hold from strb_n - t7 5 ns d_[7:0] setup to strb_n - t8 40 ns d_[7:0] hold from strb_n - t9 5 ns d_[7:0] float to valid delay from cs_n, strb_n, and a_[9:0] t10 0 50 ns d_[7:0] valid to float delay from cs_n or strb_n t11 0 10 ns figure 8. microprocessor interface timing - motorola bus mode, non-multiplexed address cs_n strb_n r/w_n a_[9:0] d_[7:0] t1 t3 t6 t5 t7 t9 t8 t10 t11 t2 t4 t3 t4
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 49 oki semiconductor microprocessor interface timing - multiplexed address parameter symbol min typ max unit ale (as) pulse width t1 20 ns a_[9:0] setup to ale (as) t2 5 ns a_[9:0] hold from ale (as) t3 5 ns reset timing parameter symbol min typ max unit reset pulse width t1 50 ns ale (as) a_[9:0] t2 t3 t1 figure 9. microprocessor interface timing - multiplexed address reset t1 figure 10. reset timing
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 50 oki semiconductor ] local clock and frame synchronization timing [1] [2] 1. timing measured with 100 pf load on all local bus outputs. 2. l_clk and l_fs shown with positive polarity, timing is equivalent when signals are inverted. parameter symbol min typ max unit l_clk period (2.048 mhz) t1a 488 ns l_clk period (4.096 mhz) t1b 244 ns l_clk period (8.192 mhz) t1c 122 ns l_clk period (16.384 mhz) t1d 61 ns l_fs delay from l_clk _ (early position) t2 -10 +10 ns l_fs delay from l_clk _ (straddle position) t3 -10 +10 ns l_fs delay from l_clk _ (late position) t4 -10 +10 ns local clock to ct bus clock skew [1] 1. when reference l_clk is more stable, there is no reduction in the amplitude of the skew, but a reduction in the number of occ urrences. the further away from the center frequency, the more frequently the skew occurs. the skew amplitude will jump in steps, but the range will remain the same. test conditions were 65.536 mhz (c_[7:4]= 0) and 2.048 mhz (c_[7:4] = 6). parameter symbol min typ max unit with c_11 (advance slave dpll timing) set to 0 (default) t5 +22.5 / -0 ns with c_11 (advance slave dpll timing) set to 1 t5 +15 / -7.5 ns local serial stream timing [1] 1. the bit cell boundary is defined by the relative edge of l_clk ( figure 11 assumes that l_clk and l_fs polarities are both non-inverted (c_[76] = 0; c_[77] = 0; c_[84] = 0; c_[85] = 0)) parameter symbol min typ max unit l_so float to valid delay from bit cell boundary t6 -10 +10 ns l_so valid to valid delay from bit cell boundary t7 -10 +10 ns l_so valid to float delay from bit cell boundary t8 -10 +10 ns 2,048mb/s sample point from bit cell boundary t9a +335.5 ns 4,096mb/s sample point from bit cell boundary t9b +213.5 ns 8.192mb/s sample point from bit cell boundary t9c +91.5 ns l_si setup to sample point t10 10 ns l_si hold to sample point t11 10 ns
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 51 oki semiconductor l_clk t1 l_fs l_fs l_fs t2 t3 t2 t4 t3 t4 ct_c8_a/b t5 t6 t7 t8 t11 t10 t9 l_so_[7:0] l_si_[7:0] figure 11. local clock and frame synchronization timing frame boundary (bit cell boundary) bit cell boundary bit cell boundary bit cell boundary
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 52 oki semiconductor h.100/h.110 clock alignment (extract from h.100/h.110 specifications, rev. 1.0) ct_frame_(a/b)_n figure 12. h.100/h.110 clock alignment ct_c8_(a/b) fr_comp_n c16 _n c2 c4 _n sclk (2.048 mhz) sclk x2* (2 x 2.048mhz) sclk (4.096mhz) sclk x2* (2 x 4.096mhz) sclk (8.192mhz) sclk x2* (2 x 8.192mhz) note: c16_n, c2, and c4_n not defined in h.110.
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 53 oki semiconductor h.100/h.110 frame structure (extract from h.100/h.110 specifications, rev. 1.0) h.100/h.110 detailed data bus timing (extract from h.100/h.110 specifications, rev. 1.0) ct_frame _(a/b)_n ct_c8_(a/b) time slot ct_dx 812345678 1 12345678 0 127 125 s figure 13. h.100/h.110 frame structure ct_frame _(a/b)_n ct_c8_(a/b) data in data out tfs figure 14. h.100/h.110 detailed data bus timing tfh 1 bit cell tfp tc8h tc8i tc8p tdod 2.0v 0.6v 2.0v 0.6v 2.4v 0.4v 1.4v tzdo tdoz tdv tdiv tsamp ts 127 bit 8 ts 0 bit 1
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 54 oki semiconductor 7.5 h.100/h.110 bus timing speci?cation (extract from h.100/h.110 specifications, rev. 1.0) parameter symbol min typ max unit notes clock edge rate (all clocks) h.100 0.25 2 v/ns [1] 1. the rise and fall times are determined by the edge rate in v/ns. a maximum edge rate is the fastest rate at which a clock tra nsitions. ct_c8_(a/b) and ct_frame_(a/b)_n edge rate h.110 0.25 2 v/ns [1] ct_netref edge rate h.110 0.3 v/ns [2] 2. 10% - 90%. test load = 150 pf. clock ct_c8_(a/b) period tc8p 122.066- f 122.074+ f ns [3] 3. tc8p min and max are under free-run conditions assuming 32 ppm clock accuracy. clock ct_c8_(a/b) high time h.100 tc8h 49- f 73+ f ns [4] 4. non-cumulative, tc8p requirements still need to be met. h.110 63- f 69+ f ns [4] [5] 5. duty cycle measured at transmitter under no load conditions. clock ct_c8_(a/b) low time h.100 tc8l 49- f 73+ f ns [4] h.110 63- f 69+ f ns [4] [5] data sample point tsamp 90 ns [6] 6. for reference only data output to hiz time h.100 tdoz -20 0 ns [7] [8] [9] 7. test load - 200 pf 8. measured at the transmitter. 9. tdoz and tzdo apply at every time-slot boundary. h.110 -10 0 ns [8] [9] [10] 10. test load - 12 pf data hiz to output time h.100 tzdo 0 22 ns [7] [8] [9] h.110 0 11 ns [8] [9] [10] data output delay time h.100 tdod 0 22 ns [7] [8] h.110 0 11 ns [8] [10] data valid time h.100 tdv 0 69 ns [7] [11] [12] 11. measured at the receiver. 12. reference only: tdv = max. clock cable delay + max. data cable delay + max. data hiz to output time = 12ns + 35ns + 22 ns = 69ns. max. clock cable delay and max. data cable delay are worst case numbers based on electrical simulation. h.110 0 83 ns [11] [13] [14] 13. reference only: tdv = max. clock backplane delay + max. data backplane delay + max. data hiz to output time = 26ns + 46ns + 11ns = 83ns. max. clock delay and max. data delay are worst case numbers based on electrical simulation. 14. based on worst case electrical simulation. data invalid time h.100 tdiv 102 112 ns h.110 102 112 ns [15] [16] 15. this range accounts for f (phase correction). 16. tcell = max. clock backplane delay + max. data backplane delay + max. tzdo + (min. tdiv - max. tdv) + max tdoz + f = 26ns + 46ns + 11ns + (102ns - 83ns) + 10ns + 10ns = 122ns. max. clock delay and max. data delay are worst case numbers based on electrical simulatio n. ct_frame_(a/b)_n width tfp 90 122 180 ns ct_frame_(a/b)_n setup time tfs 45 90 ns ct_frame_(a/b)_n hold time tfh 45 90 ns phase correction f 010ns [17]
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 55 oki semiconductor 17. f (phase correction) results from pll timing corrections. h.100. measuring conditions: data lines vth (threshold voltage) = 1.4v vhi (test high voltage) = 2.4v vlo (test low voltage) = 0.4v input signal edge rate = 1 v/ns clock and frame lines vt+ (test high voltage) = 2.0v vt- (test low) = 0.6v input signal edge rate = 1 v/ns h.110. measuring conditions: data lines vhi (test high voltage) = 2.0v vlo (test low voltage) = 0.8v input signal edge rate = 1 v/ns clock and frame lines vt+ (test high voltage) = 2.0v vt- (test low voltage) = 0.6v input signal edge rate = 1 v/ns
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 56 oki semiconductor 7.6 clock skew requirements (extract from h.100/h.110 specifications, rev. 1.0) parameter symbol min typ max unit notes (h.100) max skew between ct_c8 "a" and "b" tskc8 10 f ns [1] [2] [3] [4] 1. test load C 200 pf. 2. assumes "a" and "b" masters in adjacent slots. 3. when static skew is 10ns and, in the same clock cycle, each clock performs a 10ns phase correction in opposite directions, a maximum skew of 30ns will occur during that clock cycle. 4. meeting the skew requirements in table 2 and the requirements of section 2.3 (in the h.100/h.110 specifications, rev. 1.0) co uld require the plls generating ct_c8 to have different time constants when acting as primary and secondary clock masters. (h.110) max skew between ct_c8 "a" and "b" tskc8 10 f ns [2] [3] [4] [5] 5. test load - "a" load = "b" load. (h.100) max skew between ct_c8_a and any compatibility clock tskcomp 5 ns [1] (h.110) max skew between ct_c8_a and any compatibility clock tskcomp 5 ns [5] figure 15. clock skew requirements ct_c8_a ct_c8_b vt+ vt+ tskc8 ct_c8_a inter-operability clocks vt+ vt+ tskcomp vt- tskcomp
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ML53812-2 n 57 oki semiconductor 8.0 ML53812-2 package specifications 8.1 lqfp176 package outlines and dimensions index mark mirror finish 24.0 0.1 sq. 1.25 typ all measurements are in millimeters or degrees 26.0 0.2 sq. 0.5 0.22 0.05 1.7 max. 1.4 0.05 0 ~ 0.2 0.17 0.05 0.25 1.25 typ 144 132 89 88 45 133 176 seating plane 0.5 typ 0 ~ 10 0.6 0.15 1.0 0.2 0.10 m 0.10
n ML53812-2 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 58 oki semiconductor 8.2 lqfp176 mounting pad reference measurements 24.4 1.0 all measurements are in millimeters lqfp176-p-2424-0.50-bk 24.4 0.5 0.25
oki semiconductor the information contained herein can change without notice owing to product and/or technical improvements. please make sure before using the product that the information you are referring to is up-to-date. the outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. when you actually plan to use the product, please ensure that the outside conditions are reflec ted in the actual circuit and assembly designs. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, b ut not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in con nection with the use of product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringemen t of a third party's right which may result from the use thereof. when designing your product, please use our product below the specified maximum ratings and within the specified operating rang es, including but not limited to operating voltage, power dissipation, and operating temperature. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,of fice automation, communication equipment, measurement equipment, consumer electronics, etc.).these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medica l, including life support and maintenance. certain parts in this document may need governmental approval before they can be exported to certain countries. the purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. copyright 2000 oki semiconductor; copyright 2000 dialogic corporation. this document may not, in whole or in part, be reproduced, stored in a retrieval system, translated, or transmitted in any form or by any means, electronic or mechanical, without the express written consent of dialogic corporation or oki semiconductor. this document contains preliminary information that is subject to change without notice. while every effort has been made to en sure the accuracy of this document, due to ongoing improvements and revisions neither dialogic nor oki semiconductor can guarantee t he accuracy of printed material after the date of publication, nor can they accept responsibility for errors or omissions. dialogi c and oki semiconductor reserve the right to make changes to the product(s) described, or information contained herein, as needed. neither dialogic corporation nor oki semiconductor guarantees the suitability of the product(s) described for any particular implementation. nor does either company accept responsibility for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained herein. dialogic is a registered trademark, and ct612, scsa, scxbus, and the signal computing system architecture are trademarks of dialogic corporation. ct bus is a trademark of the enterprise computer telephony forum (ectf). compactpci is a registered trademark of the pci industrial computers manufacturers group (picmg). mvip and mvip-90 are trademarks of natural microsystems. all other names, products, and services are the trademarks or registered trademarks of their respective organizat ions. oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnishe d by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no lic ense is granted under any patents or patent rights of oki.
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